MAJORELINK=0, ESG=0, DREQ=0, INTHALF=0, BWC=00, INTMAJOR=0, START=0
TCD Control and Status
| START | Channel Start 0 (0): The channel is not explicitly started. 1 (1): The channel is explicitly started via a software initiated service request. |
| INTMAJOR | Enable an interrupt when major iteration count completes. 0 (0): The end-of-major loop interrupt is disabled. 1 (1): The end-of-major loop interrupt is enabled. |
| INTHALF | Enable an interrupt when major counter is half complete. 0 (0): The half-point interrupt is disabled. 1 (1): The half-point interrupt is enabled. |
| DREQ | Disable Request 0 (0): The channel’s ERQ bit is not affected. 1 (1): The channel’s ERQ bit is cleared when the major loop is complete. |
| ESG | Enable Scatter/Gather Processing 0 (0): The current channel’s TCD is normal format. 1 (1): The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. |
| MAJORELINK | Enable channel-to-channel linking on major loop complete 0 (0): The channel-to-channel linking is disabled. 1 (1): The channel-to-channel linking is enabled. |
| ACTIVE | Channel Active |
| DONE | Channel Done |
| MAJORLINKCH | Link Channel Number |
| BWC | Bandwidth Control 0 (00): No eDMA engine stalls 2 (10): eDMA engine stalls for 4 cycles after each R/W. 3 (11): eDMA engine stalls for 8 cycles after each R/W. |